When ratified and adopted, COM-HPC will address IIoT, edge computing, and power-/memory-intensive applications

The final PICMG ratification of the COM-HPC specification is scheduled for the first half of 2020. In the meantime, PICMG Systems & Technology has convened a brief roundtable discussion on the upcoming standard’s key technical challenges, the benefits of designing in COM-HPC, and the applications COM-HPC is most suited for.

The participants are Christian Eder, director of marketing at congatec; Stefan Milnor, system architect at Kontron America; and Jim Nadolny, engineering manager at Samtec. Edited excerpts follow.

PICMG Systems & Technology: What Industrial Internet of Things (IIoT) applications do you foresee as a good fit for COM-HPC?

Eder: Edge servers. These are located in sometimes rough environments (hot, cold, shock/vibrations, EMC). They also need high performance (i.e., 25 G Ethernet) and typical server functionalities (i.e., out-of-band management). High compute power and large memory sizes enables it to process and consolidate huge amounts of data by using AI. The COM-HPC client type will also address the typical embedded markets in industrial automation, transportation, and medical – for computer power and memory-hungry applications.

Nadolny: Industrial Ethernet and the connected car.

Milnor: I would not limit the question to what industrial applications are a good fit, but rather ask what embedded applications are a good fit for COM-HPC. And the answer to that is any application that requires high-performance computing, long life and support, high-bandwidth I/O, ruggedized characteristics, extended-temperature operation, multiple sources, and custom system form factors. Applications that are extremely cost-sensitive may not be right for COM-HPC, but it is suitable for many higher-end situations.

As such, COM-HPC will be useful in medical equipment, instrumentation, test equipment, telecommunications equipment, industrial equipment, casino gaming, transportation systems, avionics, scientific equipment, military subsystems, and likely much more. That has been the case for COM Express and will be the case for COM-HPC. COM-HPC is meant to complement COM Express, not replace it. Compared to COM Express, COM-HPC offers a significantly higher bandwidth connector (around four times higher), larger form factors supporting more powerful CPUs including server-class CPUs, more memory, more high-speed I/O options, and out-of-band management options. It will be possible to deploy COM-HPC, like COM Express, in situations requiring high shock and vibration survivability.

PICMG Systems & Technology: How do you see COM-HPC addressing key challenges facing edge computing right out of the chute?

Milnor: COM-HPC modules are ready-to-go high-performance units that can be deployed for almost any edge computing situation. The end system carrier board designer can focus on what their organization does best – whether that be medical imaging, test and measurement, gaming, telecom, etc. – and leave the core CPU design details to the module vendor. An interesting aspect of COM-HPC, not available on COM Express, is that provisions are in place on COM-HPC that allow modules to be PCI Express roots or targets, or a combination of those. This allows vendors to design COM-HPC modules that host high-end FPGAs or GPUs, useful in many edge-computing situations, such as image processing. Arm-based COM-HPC modules are also permitted.

PICMG Systems & Technology: What are some of the potential technical challenges engineers will face in their COM-HPC-based designs?

Nadolny: Server designs are expected to take advantage of the high-end features in COM-HPC and will require the use of high-speed design and fabrication practices. This includes Type 4 PCB technology (via stub-length control), low-loss PCB laminates, and attention to loss budgets. While these practices are mainstream in the datacomm market segment, they may pose new challenges for engineers unfamiliar with high-speed design. SI design guidelines are included in the COM-HPC specification to help engineers achieve first-pass design success.

Eder: Almost all interfaces received a performance upgrade which lead to much higher signal frequencies and new challenges for signal integrity. This is addressed by the COM-HPC specification and the planned carrier board design guide will also help engineers to create their carrier boards. The new interfaces like eSPI and USB4 create new possibilities which will be addressed both in the specification and in the carrier board design guide.

Milnor: To take full advantage of the high-speed I/O, designers need to be comfortable with basic high-speed PCB design techniques such as controlled impedance stack-ups and differential pair routing. Carrier board PCB design is not nearly as involved as, say, CPU module memory bus routing, but there are basic rules that need to be followed. A COM-HPC Carrier Board Design Guide is planned, and the necessary rules should be available there. Additional concerns such as proper power delivery, EMI mitigation techniques, thermal management, and other concerns should be addressed in the Design Guide as well. Most module vendors support their customers with carrier design help.

PICMG Systems & Technology: What are some areas that may need to be addressed in the next rev of the spec?

Eder: The workgroup is addressing all currently known issues. Once the first boards are designed by the member companies, we’ll ask for feedback in order fix potential undefined details in the specification with a minor update.

PICMG Systems & Technology: What are some of the benefits of going with COM-HPC over some of the competitive architectures?

Milnor: The main benefit of COM-HPC over other mezzanine-style CPU modules are the very high bandwidth COM-HPC connectors, allowance for very powerful CPUs and large memories, provision for lots of high-bandwidth I/O (up to 65 PCIe lanes, up to 8 by 25 Gbps Ethernet, etc.) and the provision for non-x86 modules, such as Arm, FPGA, and GPU modules. A benefit of COM Express and COM-HPC over backplane-based architectures like VPX and Compact PCIe is that it is easier to fit a COM module and carrier in many space-constrained systems, for example, in an autonomous vehicle or a compact piece of equipment.

Eder: Designs based on COMs are typically created for single applications and are not changed for five to 10 years. Upgrades can be performed by changing to newer COMs based on the same specification. COM-HPC will extend the range of applications – where COMs could not be used in the past – because the previous COM standards did not support 25G Ethernet, [they] only supported 96 GB of RAM or did not provide enough computer performance as the max power consumption of the older COMs did not support the energy-hungry, high-performance CPUs. COM-HPC is the newest and fastest COM standard of all and can address the performance needs of multiple new applications.

Christian Eder is a cofounder of and serves as director of marketing for EMEA at congatec. Christian – with his 30 years of experience in embedded computing – is the chairman of the COM-HPC workgroup of PICMG. He is also active in a number of PICMG working groups and functioned as editor of the following specifications: COM Express 2.0, COM Express 2.1, COM Express Design Guide, Embedded EEPROM, Embedded EAPI, and COM Express 3.0. Christian is also board member of the SGET and editor of the SMARC 2.0 and 2.1 specification. He holds a degree in electrical engineering from the University of Applied Sciences Regensburg, Germany.

Stefan Milnor – currently system architect at Kontron – has worked for Kontron and predecessor/acquired companies (Jumptec Adastra) since 1993. Stefan was the editor and author of the original COM Express specification in 2004-2005. Since then, Stefan has been a technical contributor and secretary to COM Express revision efforts. He had a major role in the COM Express and SMARC Design Guides, and was the author/Editor of the original SMARC specification. Stefan earned a BS in Physics from University of California, San Diego, and an MS in electrical engineering from University of California, Los Angeles.

Jim Nadolny, senior SI and EMI engineer at Samtec, began his career focused on the EMI design of military and commercial platform; his focus then shifted to signal-integrity analysis of multigigabit data transmission systems. Jim currently chairs a technical group within PICMG to develop SI guidelines for embedded computing platforms. Jim represents Samtec at industry standards within OIF, IEEE, COBO, and other MSAs and is a frequent presenter at DesignCon, with Best Paper awards in 2004, 2008, 2012, and 2018. He has more than 25 peer-reviewed publications. Jim Nadolny received his MSEE from the University of New Mexico.

congatec www.congatec.com

Kontron www.kontron.com

Samtec www.samtec.com