TEWS TECHNOLOGIES introduces CompactPCI Module with High-Density User-Programmable FPGA

TEWS TECHNOLOGIES announces the introduction of the TCP631, a user-programmable FPGA-based cPCI module with 1,500,000 or 5,000,000 system gates. Designed for industrial, COTS, and transportation applications, where specialized I/O or long-term availability is required, the TCP631 provides a number of advantages including a customizable interface for unique applications and a FPGA-based design to extend product lifecycle.

TEWS TECHNOLOGIES announces the introduction of the TCP631, a user-programmable FPGA-based cPCI module with 1,500,000 or 5,000,000 system gates. Designed for industrial, COTS, and transportation applications, where specialized I/O or long-term availability is required, the TCP631 provides a number of advantages including a customizable interface for unique applications and a FPGA-based design to extend product lifecycle.

For flexible front I/O solutions, the TCP631 provides a PIM Module slot that allows active and passive signal conditioning. With the TPIM003-10 all I/O signals are provided on a HD68 connector. The TCP631-2x also offers rear I/O via the J2 connector.

The TCP631 offers 64 I/O lines to the front I/O and 64 I/O lines to the rear I/O. All I/O lines are directly connected to the FPGA-pins, which maintains the flexibility of the Select I/O technology of the Spartan III FPGA. All I/O lines provide external ESD-protection devices. In addition the FPGA is connected to two banks of 128 Mbytes, 16 bit wide DDR2 SDRAM.

The FPGA is configured by a serial Flash. The Flash device is in-system programmable via driver software over the PCI bus. An in-circuit debugging option is available via an optionally mounted JTAG header on the backside of the board for readback and real-time debugging of the FPGA design using Xilinx’s "ChipScope".

A programmable clock generator provides up to four different clock output frequencies between 5 kHz and 200 MHz. All outputs are available at the FPGA – in addition, one clock source is used as the local clock signal for the PCI controller. The clock generator settings are stored in an EEPROM and can be changed by the driver software through the PCI Target Controller.

The configuration EEPROM of the PCI Target Controller can also be modified by the driver software to adapt address spaces and other critical parameters.

User applications can be developed using the design software ISE WebPACK which can be downloaded free of charge from www.xilinx.com.

Extensive software support for major operating systems such as Windows, LynxOS, Linux, Integrity, VxWorks, and QNX is available.