Open-Silicon and CoMira Solutions speed network IC development with Ethernet IP

MILPITAS, CA, August 28 – An IEEE 802.3ba-compliant 40/100G Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PCS) IP collaborated on by Open-Silicon and CoMira Solutions that can be implemented as stand-alone IP or integrated into product development has been released. When combined with Hybrid Memory Cube (HMC) or DDR3, the high performance MAC and PCS IP create a complete networking IP solution.

Co-development of the 40/100G Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PCS) IP leveraged CoMira’s high-speed Ethernet proficiency and Open-Silicon’s familiarity with IP integration and qualification, and resulted in thorough design, verification and qualification processes. Design and verification is comprised of FPGA emulation, document review, UNH compliance testing and functional and timing verification. Qualification is ensured through Open-Silicon’s proven qualification process, which is enacted upon all IP cores prior to release.

The small footprint IP and silicon development solution produces low gate counts and smaller die sizes, allowing design efficiency in devices with high port counts. It is extremely modular and highly configurable, allowing flexibility for systems scaling from 10 to 100G while supporting multiple of SerDes and interface options.

Beyond being well suited for low-latency applications, the 40G/100G MAC and PCS IP cores’ automated infrastructure enables fast system-level integration and tradeoff analysis.