News - Consortia and Working Groups
Network Equipment Providers Team to Promote Open Specifications and Accelerate Development of Carrier Grade Base Platforms
SCOPE founding companies are Alcatel, Ericsson, Motorola, NEC, Nokia and Siemens
PICMG Adds Serial RapidIO to AdvancedTCA
The PICMG 3.0 specification defines the detailed characteristics of AdvancedTCA cards, chassis, and backplanes as well as the protocol for the base interconnect between cards (Ethernet) but leaves the protocols on the extended fabric to other specifications. An add-in card must notify the system manager which fabric it supports before interconnects are enabled onto the backplane. Serial RapidIO is the latest fabric to be mapped onto AdvancedTCA.
GE Fanuc Promotes VITA 56 Mezzanine Standard Working Group
VITA 56 is a predominately PCI Express-based mezzanine board similar in dimensions to a PCI Mezzanine Card (PMC), allowing it to be used on VME and CompactPCI boards, but borrowing heavily from the functional characteristics of an AMC. These boards will be fully de-pluggable/hot-swappable without removing the carrier, will offer a level of manageability similar to AMC, and will include support for many high-speed serial fabrics.
Advanced Switching Further Expands Reach and Adoption
The Advanced Switching Interconnect Special Interest Group (ASI SIG) today announced that it continues to reach a number of industry and technology milestones. The recent introduction of ASI silicon, software, tools, and test equipment, combined with the rapid adoption of PCI Express, has expanded the ecosystem required for ASI-based storage, compute, and communications platforms. This movement has further ignited the widespread industry support of ASI technology across various platforms.
Accellera Approves New Open Verification Library Standard
Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, today announced that its Board of Directors, representing systems, semiconductor and design tool member companies, approved Accellera’s Open Verification Library (OVL) 1.0, as an Accellera verification standard earlier this month. The new standard was also approved unanimously by the Accellera OVL Verilog/SystemVerilog Assertion (OVL-VSVA) technical committee. The OVL standard results in better quality HDL (hardware description language) designs, since the pre-defined checkers, written in either Verilog or SystemVerilog, allow designers to take advantage of assertion-based verification immediately. Both SystemVerilog and Verilog language-compliant tools can take advantage of this new verification standard. The library includes 31 assertion checkers for each language that cover many of the common properties that engineers check during the functional verification of register-transfer level (RTL) code.
Service Availability Forum Announces ISAS 2006 Call for Papers
3rd Annual International Service Availability Symposium Seeks to Improve Implementation and Deployment of New High Availability Solutions