Robust AdvancedTCA systems bring bus buffers into the limelight
Christopher brings to light some overlooked aids designers of Intelligent Platform Management Buses (IPMBs) and Intelligent Platform Management Controllers (IPMCs) for AdvancedTCA systems can add to their toolboxes.
More than just capacitive isolation
Complying with I2C requirements for AdvancedTCA systems' IPMBs and IPMCs can be a challenging task. A designer must ensure that each shelf (backplane, cabling, and IPMC) stays within the 690 pF capacitive budget and that ICE signals meet rise-time requirements. Enter the I2C bus buffer, which has been recommended to help IPMCs reduce the total capacitance, as seen by the System Manager on the IPMB, by breaking the system bus into smaller, electrically isolated buses. This approach brings the designer one step closer to meeting rise-time requirements because capacitance is proportional to rise-time. However, bus buffers are providing much more than just capacitive isolation. Common AdvancedTCA applications, such as the AdvancedTCA power and signal chain shown in Figure 1, call for permitted cascading of buffers, built-in rise-time acceleration, and other system reliability functions.
These additional features provide essential functionality to any IPMB and are quickly becoming mainstays in product offerings, simply because of their continual acceptance and growing demand. Bus buffers now coming onto the market that offer low input-output offset, built-in rise-time acceleration, and stuck bus recovery will greatly aid shelf and blade designers in developing robust AdvancedTCA systems.
Early I2C buses were relatively simple, consisting of a few devices at most, confined to a small circuit board area, as Figure 2 shows. In large systems, however, a point is reached where the bus capacitance limits the speed to less than the specified amount. Bus buffers were developed to solve this problem. Since then, clever yet often not well known, features have been developed that bring important improvements to system performance, hence, the natural tendency for some system designers to overlook the importance of using bus buffers or oversimplify bus buffer selection due to the lack of understanding or exposure to new products.
IPMCs have a longer To Do list
The reasons for the recent increase in bus buffer demand go beyond why bus buffers were originally developed in the first place. Bus buffers have been used for level shifting and capacitively buffering the I2C clock (SCL) and data (SDA) signals ever since PICMG 3.0 Revision 2.0 (a.k.a. AdvancedTCA) was published in 2005. AdvancedTCA users needed a bus buffer to reside on the edge of each card that plugged into the common passive backplane and present less than 10 pF of pin capacitance, affording up to 24 cards in one system and staying under the 690 pF backplane capacitance limit. In addition, IPMCs needed to ensure that a rise-time accelerator was present on both I2C lines in order to the meet the 900 ns rise-time specification. As simple as these requirements may sound, even the simplest serial buses grew in complexity, requiring IPMCs to measure parameters including temperature and voltage, read vital product information from individual cards, and make system changes, elevating the performance needed by bus buffers.
AdvancedTCA applications are no exception to the trend for communication systems to increase in complexity while facing demands to decrease their power consumption. As a result, IPMCs become tasked with better management of the IPMBs and their respective AdvancedTCA boards. Today's applications require better cascadability of bus buffers found on multiple boards sitting along the IPMB, as well as low-voltage board support, without compromising board- and system-level reliability. An opportunity now exists to build on the original, albeit still successful, Linear Technology LTC4300A that was called out in PICMG 3.0. Rev 2.0 and take advantage of new bus buffers such as Linear Technology's LTC4307, capable of addressing the growing needs of AdvancedTCA systems.
Low offset enables cascadability
Offset voltages (VOS) are a necessary evil in many types of devices and, in this case, are always present on the I2C lines of bus buffers. Their presence allows bus buffers to have their bidirectional nature and helps identify the direction of communication on the SDA and SCL pins. More importantly, these offsets guarantee that latching does not occur on the bus. IPMCs are required by PICMG 3.0. Rev 2.0 to drive a certain amount of maximum output logic low voltage (VOL) on backplanes, while bus buffers need to accept these signals accordingly with their input logic low voltage (VIL). The low bus buffer offset voltage then becomes important when cascading bus buffers require that the preceding output low voltage plus offset voltage is less than the allowed input low voltage of the succeeding buffer or receiving IPMC. For example, in the case of an IPMC communicating through three bus buffers to another IPMC, designers must ensure:
VOL(n) < VIL(n+1), where VOL(0) = VOL of the master IPMC, and VOL(n) = VOL(n-1) + VOS(n-1).
Cascading bus buffers with low input-to-offset voltages will then allow IPMBs to expand with more peripherals and longer bus lines.
AdvancedTCA designers know that IPMC ICs drive logic low voltages much smaller than what is specified in their data sheets. Unfortunately, it is common practice for CPU manufacturers to simply copy the I2C specification's electrical table into the data sheets to easily show compliance. As a result, some designers question the ability to cascade bus buffers for fear of violating the VIL threshold of bus buffers, especially towards the receiving end of the signal chain, and are surprised the buffers take to cascading without any problems. This is because IPMC ICs realistically drive logic low voltages as low as 50 mV. For example, this 50 mV combined with a bus buffer offset, of say 60 mV (typical) as found in the LTC4307, results in an output logic low voltage of 110 mV for the next bus buffer to accept. Figure 3 shows a rising edge transition displaying low input-output offset voltage. The offset voltage is small enough that, with the LTC4307's logic low input of 480 mV, designers are able to cascade up to seven bus buffers if needed, a task that would be more difficult if the designer is using older generations of bus buffers with lower logic low input voltages and higher offset voltages.
Rise-time acceleration meets IPMB rise times
The I2C bus lines idle high, pulled up by resistors to the supply voltage, while IPMCs and other controllers on the IPMB transmit by pulling the lines low. PICMG 3.0 Rev 2.0 calls for both the SCL and SDA signals to rise monotonically from 1 V to 2.3 V in 900 ns with a 2.7 kilo-ohm pull-up to 3.3 V and a 690 pF load. This task requires using some kind of active circuitry to accelerate rise times, and is where the additional current sources provided by Rise-Time Accelerators (RTAs) come in handy.
The LTC4307's built-in RTAs provide strong, slew-limited pull-up currents to meet rise-time requirements. After initial rising edge conditions, the accelerators are automatically activated during positive bus transitions and make the bus voltages rise at a rate of 100 V/microsecond on all four SDA and SCL pins. This automatic activation of the accelerators significantly improves board and system reliability in a number of ways. First, the accelerators provide smooth, controlled transitions during rising edges. The accelerator pull-ups present impedances significantly lower than bus pull-up resistances, making the AdvancedTCA systems much less susceptible to noise on rising edges. Second, the accelerators permit the use of larger bus pull-ups, which reduce power consumption and improve logic low noise margin. For lightly loaded systems where fast slew rates can cause transmission line reflections on the bus, the LTC4307 throttles down the pull-up current when edges rise faster than 1 V/10 ns. The RTAs are automatically deactivated when holding logic highs, on falling edges, and during automatic clocking or stop bit generation.
RTAs are available both as separate, discrete accelerators and as built-in RTAs that are integrated with their bus buffer counterparts. RTAs integrated with their bus buffer counterparts increase convenience by giving slew rate detection and adjustments to both sides of the bus buffer. It would not matter which IPMCs on the bus are tasked with meeting the rise-time requirements; bus buffers throughout the IPMB accelerate all of the intermediate buses, rather than accelerating each node individually when using discrete solutions.
It is advised to use RTAs in most instances, except in systems that use very strong pull-ups or exhibit low bus capacitance. Under these conditions, the accelerators can turn small noise perturbations into rail spikes when falsely triggered. In applications where no rise-time acceleration is used, strong pull-up resistors are needed to ensure rise-time requirements are met. However, this is easier said than implemented, especially in lower voltage systems where stronger pull-ups correspond to smaller voltage drops across the resistors, thereby decreasing the output logic low voltage margin. Figure 4 compares I2C waveforms for RTAs versus pull-up resistors.
In addition, IPMCs need to sink 1.2 mA to ground while abiding by the maximum logic low output voltage needed to drive I2C signals. In other words, although some bus buffers do not offer rise-time acceleration and can claim AdvancedTCA compliance, it is unfortunate that compliance does not always translate to a healthy IPMB in both large and small systems. Therefore, it is recommended to use bus buffers with built-in rise-time acceleration that can both claim compliance and further reduce component count, complexity, and cost, especially in heavily loaded, low voltage systems.
Reliable IPMC hot swapping
Bus controllers are required to present a high impedance state to the IPMB when unpowered and powering up, a requirement that was written specifically with hot-swapping in mind. The LTC4307 accomplishes this task with its low input capacitance of less than 10 pF, minimizing bus disturbance during hot swap operations. The LTC4307 also features ¬±5 kV human body model ESD protection. Because bus buffers are commonly placed at the forefront of the I2C signal path of an AdvancedTCA board, rugged ESD structures can help reduce damage to the IPMC during hot swap activities. In addition, during start-up, the LTC4307 monitors both the IPMB and card-side bus for either a stop bit or idle condition before the input-to-output connection circuitry activates, ensuring absolutely no disturbance is made to other AdvancedTCA boards on the bus. Moreover, a 1 V precharge on all SDA and SCL lines also minimizes the worst-case voltage differential these pins will see upon live insertion of the board into the live IPMB.
Stuck bus detection and recovery fosters dependable buses
Unfortunately, even operation of the I2C bus used by IPMBs in AdvancedTCA systems has its flaws, including running into a "stuck" bus situation. Slave devices use the clock signal, SCL, to sample data on the bus and occasionally become confused, holding the SDA line in a low state unnecessarily. This could be due to a number of reasons. Most of the time, a slave is waiting for additional clock cycles issued by the master and, for some reason, does not receive them. A faulty master might not properly transmit all of the clock cycles, or perhaps a start or stop bit may have been distorted along a noisy IPMB. Maybe the slave is simply faulty. Whatever the culprit, there are many causes, and stuck buses do occur under even the most unlikely environments and conditions. If not corrected, a stuck device prevents other devices on the bus from communicating until the stuck device releases high. Therefore, it is in the best interest for board designers to provide healthy data transmission on the IPMB by using some kind of stuck bus recovery technique.
Bus buffers like the LTC4307 have implemented stuck bus detection and recovery circuitry to address stuck buses (Figure 5, shown without the FAULT pin). This is done by monitoring the outputs of both SDA and SCL pins independently for a stuck bus condition and triggering an internal 30 ms timer if a low state is detected. The timer only resets if the bus returns high within the allotted amount of time. Otherwise, the input-to-output connections for both I2C signals are broken, preventing further communication with the stuck device. The bus buffer then generates up to 16 clock pulses at 8.5 kHz on the SCLOUT in an attempt to free the card-side stuck bus. If the bus unsticks or if the 16 clock pulses are completed, a stop bit is generated to clear the bus for further communications and the input-to-output I2C connections are reconnected.
The LTC4307 features an ENABLE pin that can force reconnection of the bus after disconnection of a bus due to a fault condition. This would be handy if a master were to manually attempt to free the bus. For board designers looking for more control over their stuck buses, more advanced bus buffers like the LTC4309 feature a FAULT pin to indicate when a stuck bus has been detected, as well as a DISCEN pin to disable the input-to-output disconnection function of the stuck bus recovery feature entirely.
Designers should take advantage of the benefits new bus buffers bring to AdvancedTCA systems. These advantages include:
- The ability to break a large, unmanageable bus into several manageable buses
- Cascading bus buffers more easily
- Providing vital rise-time acceleration needed to ensure low voltage systems are PICMG 3.0 compliant
In addition, a host of other features allows designers to account for unpredictable system hiccups and promote continuous uninterrupted operation. These include:
- Stuck bus recovery
- Precharging of the I2C lines
At the end of the day, bus buffers can simply be purchased for the capacitive isolation they provide, but AdvancedTCA designers now have more confidence that the bus buffer will greatly aid its neighboring IPMC in the management of a healthy IPMB.