Racing to test next-gen mobile: Inside track for AdvancedTCA?

Modularity and interoperability poise AdvancedTCA solution architecture as the favorite to meet the burdensome demands of LTE telecommunications test equipment.

3Test equipment manufacturers increasingly find themselves in time-to-market races where they feel the eyes of all those counting-on-five-nines users on them. Tom outlines here what's needed for the challenges of this race and evaluates what kind of racing form AdvancedTCA brings to the contest.

One of today’s most demanding applications is testing next generation mobile communications. At any point in time hundreds of mobile phone calls can occur within the range of any given cell tower, and every user expects a reliability of 5-nines (99.999 percent) or higher. Long Term Evolution (LTE) telecommunications test equipment must be powerful and flexible enough to simulate new generations of handsets with a wide range of behavior. Such equipment must also test the real-time data throughput of millions of voice and data calls. Without such insight and monitoring, telecom providers cannot maintain network performance and deliver on Service Level Agreements (SLAs).

Programming test equipment to accurately simulate future services as they encounter anticipated voice and data traffic is a must for telecom providers. Developers of telecommunications test equipment can stay ahead of the curve by building flexibility and scalability into systems that are well capable of the advanced processing sophisticated simulations demand.

An AdvancedTCA solution architecture, implemented with a Serial RapidIO data plane, addresses this challenge (Figure 1). Take the need for scalability, for example. The AdvancedTCA architecture is scalable, with system configurations ranging from two to a hundred or more AMC-based processing elements. When populated with various kinds of processors, the AMCs can enable each simulation algorithm to match the type of processor that delivers optimal performance. Serial RapidIO links together the simulating processors to bring about high-bandwidth, low latency, and deterministic interprocessor communications.

Figure 1: A RapidIO-based AdvancedTCA architecture allows for a great degree of scalability and flexibility.

Proper matching for processing power efficiency

Different processing elements, such as FPGAs, DSPs, and network processors, are designed to handle different processing requirements. Standard general-purpose processors, Digital Signal Processors (DSPs), and Field-Programmable Gate Array (FPGA) processors each specialize in a particular type of processing, and some work more successfully than others for a given processing problem. If an application is processing-intensive but does not have properly matched processing technology, it may need more processing power than it otherwise would.

FPGAs are most effective for simple mathematical operations such as add/multiply. When performing add/multiply and other basic tasks, FPGAs carry out the operations at the gate level as the data moves through. Unlike FPGAs, other types of processing elements must move the data from memory to a computational unit and back. For beamforming applications, which require an enormous number of simultaneous mathematical calculations, FPGAs are far superior to other processor types. Operations that can be performed with Boolean logic are best done on FPGAs. FPGAs are also good for filtering operations, which pull wanted desirable data from an incoming data stream or remove unwanted data. For example, in applications that process antenna-generated data, an FPGA can efficiently filter out carrier information from incoming data channels.

DSPs, on the other hand, are very effective for data compression and decompression (codec) operations. In addition, applications often combine compression and decompression of data using a pipelined process with echo cancellation operations, another DSP strength. Echo cancellation is a critical component of Voice over Internet Protocol (VoIP) technology. For codec operations, DSPs perform significantly better than standard processors or FPGAs.

Network processors, which are specialized programmable Application-Specific Integrated Circuits (ASICs), are best for in-depth packet analysis. The format of a packet is clearly defined, so the desired information can be extracted efficiently. A network processor in a router, for example, defines in real time:

  • Where to send an incoming packet
  • What its priority is
  • How promptly it needs to be processed

The network processor functions just mentioned and similar functions are based on in-depth analysis of the packet content.

When different types of processing must be applied to a data stream, it makes sense to match processing elements to specific processing needs. For example, in voice and video applications, the DSP engine compresses the data, while the network processor on the router identifies packets as voice or data-only, assigns a higher priority to voice packets, and sends them out on the network. Or, in a voice processing application, an FPGA does waveform processing of the input signal from the antennae, while a network processor behind the FPGA performs packet-level processing.

Latency and determinism

Latency and determinism are critical characteristics of telecommunications test processing requirements. Processing latency – where latency is units of time measured from ingress port to egress port – must be very low. The parameters that define a low-latency response depend on the application. For example, voice processing applications must control the signal processing delay across the entire network, including both satellite transmission delays and intra- and inter-system processing delays, to make a phone call understandable. The goal is 200 to 250 milliseconds of maximum delay end-to-end, which must be accurately simulated in the test equipment.

These very low latencies must also be reliable. For the application to perform properly, each data processing step must be performed within a clearly defined, extremely small window of time, and this window must be the same each time the step is performed. This characteristic, referred to as determinism, requires the consistent, reliable, and highly predictable data movement Serial RapidIO makes possible.

The RapidIO protocol was designed specifically for embedded applications, supporting chip-to-chip and board-to-board communications. RapidIO delivers communications with high bandwidth, low latency, determinism, and limited software dependence. Most of the RapidIO protocol is implemented in the hardware of its endpoints, simplifying software support and reducing software overhead.

The case of the LTE test system

Addressing a challenge with AdvancedTCA telecommunications test equipment requires expertise and experience in data plane integration, using combinations of general-purpose processors, DSPs, and FPGAs. For example, to achieve high bandwidth and low latency, a Japanese leader in 3G/LTE Radio Access Network (RAN) testing recently developed an LTE test system that established a new testing capacity standard.

In this test system a 14-slot AdvancedTCA chassis (Figure 2) forms the base platform, though configurations can be scaled down based on customer requirements. A pair of Serial RapidIO switch blades moves data between processors with maximum efficiency using a dual-star switching topology over the backplane. AdvancedTCA carrier blades, each hosting four AMCs, and a specialized processing blade with FPGAs and DSPs fill out the rest of the slots. To perform the processing, the AMCs sited on the carrier blades use a dedicated Mercury MTI-203 TI DSP AMC and an MPC102 dual-core 8641D AMC.

Figure 2: A 14-slot AdvancedTCA chassis, the Mercury Ensemble 8000.

The result is a very high-capability product test system for telecommunications equipment. Robust system configurations like this can be built using Mercury’s Ensemble 8000 AdvancedTCA or Ensemble 2000 MicroTCA application platforms. These systems all support high-bandwidth backplane data movement with the RapidIO switch fabric, connecting carrier blades, switch blades, system software, and a wide range of processor-based AMCs. The set of processor-based AMCs includes Xilinx FPGAs and TI DSPs as well as PowerQUICC and PowerPC 8641D processors. Application developers can use the platforms to combine extreme processing density with low-latency, deterministic communications.

Race strategy: it takes a village

With technologies on the racing team that include multicore processors, the latest DSPs and FPGAs, and Serial RapidIO interface, AdvancedTCA can perform to the level required to meet rigorous LTE telecommunications test equipment demands. The result is a modular system that can handle applications simulating the latest wireless networks.

Tom Roberts is a Solution Marketing Manager at Mercury Computer Systems. He joined Mercury in 1999 and has more than 20 years of experience in systems engineering and technical marketing with IBM, Nixdorf, Data General, Digital Equipment, and Compaq. Tom has a bachelor’s degree in engineering from Cornell and a master’s degree in business from the University of Kansas.

Mercury Computer Systems