Pairing CompactPCI compatibility with high-speed serial data transfer

All-or-nothing dilemma

One unfortunate side-effect of technological advancements is that they often force end users to accept an “all-or-nothing” choice between a major investment in enhanced speed and capability, or living with less-than-optimum performance to protect the investment in an installed technology base. At best, there’s the troublesome option of supporting two technologies in tandem for a period of time as newer equipment gradually replaces older hardware.

However, a solution is on the horizon for the many embedded system users who rely on the popular CompactPCI interface. The PICMG CompactPCI Plus subcommittee of more than 20 participating companies is developing two distinct specifications to allow users to make a smooth transition to improved, yet 100 percent compatible, extensions of well-established CompactPCI specifications. These two draft specifications are the PICMG 2.30 CompactPCI PlusIO specification and the PICMG CPLUS.0 specification.

The PICMG 2.30 effort focuses on replacing CompactPCI parallel bus architecture limitations with the greater flexibility of serial point-to-point connections. At the same time, consistency in pin assignments is preserved to ensure hardware compatibility among modular boards and backplanes from various manufacturers. The resulting specifications will serve CompactPCI system users by allowing them to incorporate the new interface enhancements into existing applications and streamline development of new applications that don’t need to integrate with existing CompactPCI hardware.

Star topology

Unlike other serial transmission structures that use more complex switched fabrics for I/O, the CPLUS.0 CompactPCI Plus draft specification uses a star topology connected by serial point-to-point connections. The system slot is the center of the star, and each peripheral board is a symmetrical point.

This simple and inexpensive approach, available in both commercial and rugged designs, offers flexible high-speed performance without the higher costs of switched fabric technologies. And it builds in compatibility for multiple interface formats associated with a variety of popular peripheral functions, such as:

PCI Express (PCIe) interfaces for connecting close peripheral devices

SATA/SAS interfaces for mass storage devices like hard disks and hard-drive RAIDs

USB interfaces for WiFi components and loosely coupled peripheral devices like keyboards, touch screens, and external hard disks

Ethernet interfaces for traditional network technology as well as for multiprocessing and as a fieldbus for decentralized I/O

The new peripheral slot and connector have been defined for differential signals with fast data rates of at least 10 Gbps to support next-generation serial buses such as SATA 3.0, PCIe 2.0, 10GBASE-T Ethernet, and USB 3.0.

In all cases, the mechanics are IEC 1101-compliant and fully compliant to the PICMG 2.0 CompactPCI specification. The dimensions of backplanes and boards are identical to PICMG 2.0, as are the front panels and the hot-plug mechanics.

Addressing application needs – old and new

The new CompactPCI Plus interface promises higher computing performance for robust applications while maintaining 100 percent compatibility between older and newer platforms. While the end result is common, two separate draft specifications bring it to fruition for different application scenarios.

PICMG 2.30 CompactPCI PlusIO

This supplement to the PICMG 2.0 specification sets forth a migration path to upgrade existing parallel CompactPCI hardware to serial CompactPCI Plus performance (Figure 1). It defines the functions of user pins on a modified J2 connector for backplane I/O signals of the serial high-speed interconnects. And it introduces a fully compliant high-speed connector capable of using all backplane I/O pins for high-speed signals without adding additional ground pins.

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Figure 1

With a dual-slot CPU, it is possible to use the new system slot to build a hybrid system. And with a suitable hybrid backplane, both CompactPCI and CompactPCI Plus boards can be run in the same system (Figure 2). This will allow applications to take advantage of an investment in existing I/O boards wherever practical, while allocating functions with higher data transfer rates to the newer CompactPCI Plus boards.

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Figure 2

The working group finalized the initial draft of the PICMG 2.30 CompactPCI PlusIO specification at the end of 2008. That draft specification is under review for final approval. As proposed, the specification allows for up to four new serial interfaces to be added to an existing CompactPCI installation.

PICMG CPLUS.0

Also currently in development, the PICMG CPLUS.0 draft specification is for building entirely new applications and offers performance advantages for end-use applications where there is no need to interface with existing CompactPCI hardware.

The new PICMG CPLUS.0 system slot allows up to eight additional peripheral interfaces to be added without the need for additional switches or bridges (Figure 3). And it specifically supports full-mesh Ethernet connections for a primary board and eight additional boards to allow for symmetrical multiprocessing and redundant system applications. The draft specification also defines ground pins between the signal pins, following a dedicated pattern, so there are no special ground pins in the connector.

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Figure 3

New connectors

Two of the performance enhancements in the new CompactPCI Plus draft specifications revolve around newly specified connectors capable of handling the upgraded speed and performance.

For PICMG 2.30 applications, the challenge was to find a connector that was mechanically compatible with the original CompactPCI 2 mm Hard-Metric (HM) connector, yet could satisfy the transmission speeds modern serial interfaces require. The selected solution is a 3M Ultra Hard Metric (UHM) connector with virtual coaxial box shielding to significantly reduce the crosstalk commonly experienced at 1.0 to 1.5 Gbps speeds in current CompactPCI installations. In fact, the new connector is rated for speeds of 7 Gbps even when mated with the standard unshielded 2 mm HM headers. This new connector makes PCI Express, SATA, USB, and Ethernet available on the backplane alongside the legacy CompactPCI bus.

For PICMG CPLUS.0 draft specification applications, the design of FCI’s AirMax VS connector system, which supports data transfer rates of up to 12 Gbps, is the proposed backplane connector standard. The shieldless high-speed connector consists of Insert Molded Leadframe Assemblies (IMLAs) mounted at a pitch of 2 mm. This format offers up to 184 pin pairs on a 3U board.

In the PICMG CPLUS.0 specification, the receptacles are mounted on the backplane and the pins on the plug-in cards. This arrangement is more robust than the legacy CompactPCI design, minimizing potential damage due to bent pins when inserting cards into the backplane. And in the event of a connector pin failure, it is not necessary to remove and replace the entire backplane, but only to replace the individual plug-in card.

Enhanced applications on the horizon

New applications requiring considerably more bandwidth, storage capacity, data management capabilities, and real-time functionality consistently place increased demands on embedded computing systems, especially as they go mobile in harsh environments. These include video surveillance, industrial automation, automotive testing, diagnostics, and human-machine interfaces.

Even in such demanding applications, versatile mezzanine cards for high-end graphics and communications supported by high-speed CompactPCI Plus technology delivered in a proven modular format create opportunities to make this interface a very attractive option for leading-edge embedded system designers.

Robustness – Multiple features of the CPLUS.0 format – a plug-in concept on a passive backplane, a small format, and the shock-resistant/vibration-resistant design of a traditional 19" chassis offering multiple options for effective convection and conduction cooling – make it a well-positioned option for industrial, mobile, and harsh environment applications.

Scalability – Opportunities to add new boards as computing or I/O requirements increase addresses applications with fluctuating demands.

Minimized risk – The power to build complex clusters and redundant systems provides the confidence for safety-critical control system applications such as nuclear power stations, medical equipment, railway control, and surveillance systems.

Convenient maintenance – The user-friendly modular design of the familiar 19" chassis and plug-in board format, complemented by hot-swap capability, supports quick, cost-efficient maintenance in highly demanding applications where extended downtime conditions are unacceptable.

Long-term availability – While not all individual manufacturers will guarantee availability of 10 years or more, the familiarity of the CompactPCI specifications increases the likelihood of available, compatible, off-the-shelf assemblies for system replacements or upgrades.

Manfred Schmitz Technical Director, MEN Mikro Elektronik, can be contacted at

manfred.schmitz@men.de

Roland Nuiten, Application Engineer, Electronic Solutions Division at 3M Deutschland GmbH,

can be contacted at rnuiten@mmm.com