CompactPCI flag still waves high in military/aerospace applications

3Technology platforms have recently gone through another iteration of upgrades and enhancements to keep them viable for the long term in military and aerospace applications. Tried-and-true parallel bus architectures have been revamped to accommodate application demands in the rugged, harsh worlds of military and space, with CompactPCI (CPCI) remaining the platform of choice for many defense and aerospace applications.

Some recent industry articles have claimed that high-speed serial fabrics are replacing “data throughput and speed challenged” parallel buses like CPCI, even in applications that are primarily event driven. These types of hard-deadline operations are typically tight, deterministic behavior, servo control-loop applications, and include reading position sensors and controlling motors and linear actuators, moving gun turrets and missile launch frames into position, and stabilizing camera or heavy gun platforms. A parallel bus interrupt-driven structure with minimal latency is the only architecture that can handle these kinds of applications in real time.

Parallel’s prevailing purpose

Parallel buses are, by definition, synchronous data buses with bus message formats and often dedicated instructions – including Read-Modify-Write – that “lock” the bus so that critical messages arrive in order and are synchronized in process and in time. Serial fabrics cannot yet replace parallel buses in closed-loop feedback systems, as none of these fabrics possess the real-time response capability needed. Serial fabrics are ideal for Command, Control, Communications, Computers, Intelligence, Surveillance, and Reconnaissance (C4ISR) applications where passing massive quantities of data between predefined points in a system or platform at high speeds is needed for post processing, but if data is generated and passed throughout a subsystem platform via a multi-drop network – as with Ethernet and TCP/IP – packets can, and most likely will, get out of sync.

TCP/IP has sufficient packet overhead to ensure data is re-assembled in the correct order, thus ensuring data integrity. On parallel data buses like CPCI, synchronous, application-specific commands always occur – in time and in sync – and the use of interrupts ensures real-time performance. In current multi-pipe serial fabrics, since there is no strong data typing and encapsulation, multiple data packets can easily arrive out of sync due to network overload, protocol overhead, and processor and network latencies so that commands like “Ready, Aim, Fire” arrive as “Ready, Fire, Aim.” It can also result in uncommanded motion in large vehicle hydraulic servo loops, which then represents a safety hazard and presents a real risk to operators.

System engineers are only now recognizing and grappling with the effects of these “out-of-sync” messages and their unintended consequences. Real-Time Operating Systems (RTOSs) also now have to deal with multicore parallel processor models and multiple parallel data streams, all of which affect system architectures and application software design. For this reason, many system integrators for event-driven apps are choosing a hybrid approach to systems design by mixing the power, performance, and raw speed of high-speed serial data pipes with parallel buses like VME or CPCI for control loops. As part of the technology upgrade process, these issues will certainly be solved in the standards communities in the fullness of time, but the pitfalls need to be identified in the short term. Until then, small, compact real-time systems need deterministic parallel backplanes; it’s as simple as that.

CompactPCI in aerospace/defense

With almost a quarter century under its belt, CPCI has not only a large installed based of embedded computing systems, but also a wide-ranging network of designers that know its ins and outs, making it an easy-to-integrate platform. Like all industry standard products, CPCI has adhered closely to the PICMG, IEEE mechanical, and VITA conduction-cooled standards. But while other bus architectures and technologies focused on larger board form factors (for example 6U and 9U), CPCI found a home with small form factor 3U mechanical standards.

Unlike original Eurocard solutions, such as VME, that use connectors with a 0.1" (2.54 mm) pin spacing, CPCI cards use metric-based connectors with a 2 mm pin spacing designed to the IEC 1076 standard. Upon CPCI’s inception, this offered higher pin densities than competing standards, thus providing more backplane pins for the main system bus and dedicated user I/O. Consequently, 3U CPCI became an ideal choice for platforms and applications that require small relative module sizes and a modular and flexible system architecture.

In general, the smaller the board and the subsequent chassis subsystem’s form factor, the easier it is to fit the system into smaller spaces in satellites and manned/unmanned vehicles, and CPCI subsystems have found a niche in many of these harsh, mobile, and compact applications. Of course, the embedded ecosystem needs more than just CPCI as a technology platform, and ­­there are certainly applications better suited to other standard technologies. But for the short term, CPCI remains an exceptionally viable platform for executing highly integrated computing functions for military and space-based platforms.

In the trenches

For the military, 32-bit 3U CPCI provides a compact form factor and the available backplane I/O pins needed for system flexibility.
As a result, the 3U CPCI form factor has found a home in many applications where 3U VME could not provide the required backplane I/O, for example in many of today’s modern rotary- and fixed-wing aircraft.

Other applications that rely heavily on the small footprint and available backplane I/O afforded by CPCI include lightweight, low-power mission computers, remote intelligent display processors, and audio/intercom controllers on tactical and strategic aircraft and mission computers for hypersonic cruise missile prototypes. Even advanced “Star Wars” prototype vehicles and their test platforms utilize 3U CPCI because of its roots in known entities such as PICMG, IEEE, and VITA.

CPCI to the stars

The space community relies almost exclusively on both 3U and 6U CPCI because of the inherent mechanical ruggedness of the form factors, the 2 mm connector pin and socket connector ruggedness and pin density, as well as the relatively large amount of available onboard real estate when using today’s modern and highly integrated RISC and DSP microprocessors. For the space market, the 2 mm CPCI connector is also available in an even more rugged “full wrap” pin and socket construction versus the older, more easily mass-produced (and therefore less expensive) box and blade mated connector pin style.

Rad-hard and real-time space requirements

As in the past, the aerospace community is in search of computing platforms and processor modules that can meet the immediate and future demands of space travel. The aerospace industry is pushed to provide more onboard processing and data storage capabilities for high-bandwidth, real-time data from various types of advanced remote sensors. Typical mission-critical space system applications will also require advances in core processing elements, including:

  • Mission computers with or without redundancy
  • Remote sensor or command/control platforms
  • Flight guidance and navigation computers
  • Solid-State Mission Data Recorders (SSMDRs)
  • Health monitoring computers
  • Robotic vehicle and manipulator controllers

Moreover, a design engineer needs processing power and I/O flexibility that meet or exceed what is available on their desktop, and is at least on par with contemporary military-environment embedded processor modules. And with the requirement for maximum technology reuse across multiple systems in satellites and space vehicles – from the avionics suite to payload packages – settling on a processor module that meets multiple system requirements simplifies the overall design task and maximizes investment against the harsh nuclear and particle effects of space.

Emergence of COTS rad-tolerant boards for space

For Earth-orbit and deep space missions, open standards-based system architectures like CPCI have enabled an approach based on modularity and flexibility in a “system of systems” design (Figure 1). Unlike in the Apollo program – where proprietary processors, remote data concentrators, network servers, and subsystems were designed from scratch – modern COTS technology can meet NASA’s space demands as long as appropriate attention is paid to mitigating space environmental effects such as Total Ionizing Dose (TID), Single Event Effects (SEEs), and error recovery during the design phase.

Figure 1: Prior to program cancellation, a single-slot CompactPCI SBC was included in the Ares I launch vehicle’s Instrument Unit Avionics (IUA) Flight Computer (FC) to relay high-speed imaging data to the Crew Exploration Vehicle’s (CEV’s) solid state recorder and ground support system.

There are now well-understood redundancy and mitigation techniques in designing a radiation-tolerant SBC board. Many individual techniques have been introduced in the past, but are now combined to provide integrated radiation hardness enhancements at the board-level. At Aitech, for example, all CPCI products for space are tightly controlled in terms of components selection, procurement, use, manufacturing process controls, counterfeit component risk mitigation, component obsolescence control, and long-term storage (Figure 2).
These processes and procedures are approved by customers and the NASA Parts Selection List (NPSL) for Electrical, Electronic, and Electromechanical (EEE) components selection and usage for manned space flight – the highest NASA standards in component/parts control.

Figure 2: Overall design is simplified when using a proven technology with a large installed base, such as CompactPCI maintains with a variety of 3U board options.

Further, by incorporating dual footprints for various components into the design, state-of-the-art SBCs can be made available as an engineering unit that is a form-fit-functional equivalent to the flight unit. The engineering design units allow for rapid prototyping of space missions with software compatibility for flight configuration. Users’ environmental and operational requirements for various space environments can be met by two different flight configurations on the processor card.

In it for the long haul

Any new processor in an embedded system design today must target the current and future needs of affordable yet higher performance open architecture computing platforms for ground, avionics, and space-borne subsystems. With this, bus architecture selections represent major investments in not only hardware and software, but also in logistics and long-term maintenance infrastructure. Architectures can’t be arbitrarily set aside just because a new, untried, or untested competing bus topology with a fundamental shift in command-response control systems is implemented.

In some cases, the selection of CPCI or another standard bus represents a personal preference by the customer base – a decision or an investment that is difficult to change, especially when the bus architecture chosen continues to meet the mission parameters successfully. Like the selection of RISC or DSP processor family, it sometimes just comes down to a “Motherhood and Apple Pie” issue that won’t change until its time has come. In the area of military, defense, and space applications, critical functions need to be tested reliable before they’re implemented to ensure human safety on many different levels. Newer embedded computing platforms need time to be integrated, tested, and proven before making large scale inroads into existing technology programs. It is for this reason that the CompactPCI standard will remain a viable technology platform for military and space applications.

Doug Patterson is Vice President,
Military & Aerospace Business Sector
at Aitech Defense Systems.

Aitech Defense Systems