In the past, simulation studies have played a vital role in developing both the 33 MHz PCI standard and the 33 MHz CompactPCI standard. Existing 33 MHz PCI bus interfaces have been run at 66 MHz with point-to-point signal connections between two devises. However, 8-slot CompactPCI backplanes do not run reliably at 66 MHz due to the drive limitations of existing PCI silicon and the tighter bus timing requirements of 66 MHz operation. Recent simulation studies by AMP Incorporated have focused on determining the maximum number of board slots that can be supported reliably on a 66 MHz Compact PCI backplane. In this article, Robert describes how these studies were done, and summarizes the simulation results.
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