PCI technology (upon which CompactPCI bus is based) is a power-saving CMOS technology. While this does simplify some system design issues (such as thermal dissipation) it does not relieve the designer of the need to carefully design the DC power distribution grid. In particular, the CompactPCI backplane designer must consider the effects of transient loads on the power distribution grid, and must incorporate features to mitigate their potentially deleterious effects. In this article Andreas explains the source of these transient loads, discusses various methods for mitigating their effects, and points out some pitfalls to avoid. He then presents empirical data (in the form of scope traces) to demonstrate the effectiveness of these methods.
